INTSTAT

         This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled, serr_req signal will be asserted.
      
Module Instance Base Address Register Address
ecc_emac1_tx_ecc_registerBlock 0xFF8C0C00 0xFF8C0C20

Size: 32

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

DERRPENB

0x0

Reserved

SERRPENB

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

DERRPENA

0x0

Reserved

SERRPENA

0x0

INTSTAT Fields

Bit Name Description Access Reset
24 DERRPENB
Double-bit error pending PORTB.
RW 0x0
16 SERRPENB
Single-bit error pending for PORTB.
RW 0x0
8 DERRPENA
Double-bit error pending for PORTA.
RW 0x0
0 SERRPENA
Single-bit error pending for PORTA.
RW 0x0