bridge_tcu_mprt_3_70_SYSCOREQ_reg 

         TBD
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF702FF70

Size: 64

Offset: 0x2FF70

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

UNSD

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

UNSD

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UNSD

RO 0x0

REQ_REG

RW 0x1

bridge_tcu_mprt_3_70_SYSCOREQ_reg Fields

Bit Name Description Access Reset
63:1 UNSD 
                 -: Unused
RO 0x0
0 REQ_REG 
                 -: Request
RW 0x1