intrgen 

         Global Interrupt Enable

Writing 0 will disable any functions from this IP to cause a hardware interrupt.
Interrupt pending status register can still be set but the hardware interrupt signal will remain de-asserted.

Writing 1 will enable the hardware interrupt from this IP.
Module Instance Base Address Register Address
i_clk_mgr_clkmgr 0xFFD10000 0xFFD1000C

Size: 32

Offset: 0xC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

en

RW 0x0

intrgen Fields

Bit Name Description Access Reset
0 en 


                     		

                     
                        RW
                     

                     
                        0x0