PWREN

         Power Enable Register
      
Module Instance Base Address Register Address
sdm_i_sdmmc_sdmmc_block 0xFF8D1000 0xFF8D1004

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

POWER_ENABLE_0

RW 0x0

PWREN Fields

Bit Name Description Access Reset
0 POWER_ENABLE_0
Power on/off switch for up to 16 cards; for example, bit[0] controls card 0.Once power is turned on, firmware should wait for regulator/switch ramp-up time before trying to initialize card.
                                                0-power off
                                                1-power on
                                                Only NUM_CARDS number of bits are implemented.Bit values output to card_power_en port. Optional feature; ports can be used as general-purpose outputs.
Value Description
0x0 Power off
0x1 Power on
RW 0x0