sbcr

         Shadow Break Control Register.
      
Module Instance Base Address Register Address
i_uart_0_uart_address_block 0xFFC02000 0xFFC02090
i_uart_1_uart_address_block 0xFFC02100 0xFFC02190

Size: 32

Offset: 0x90

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_sbcr_31to1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_sbcr_31to1

RO 0x0

sbcr

RW 0x0

sbcr Fields

Bit Name Description Access Reset
31:1 rsvd_sbcr_31to1
Reserved bits [31:1] - Read Only
RO 0x0
0 sbcr
Shadow Break Control Bit.
This is a shadow register for the Break bit (LCR[6]), this can be used to remove
the burden of having to performing a read modify write on the LCR.
This is used to cause a break condition to be transmitted to the receiving device.
If set to one the serial output is forced to the spacing (logic 0) state. When not
in Loopback Mode, as determined by MCR[4], the sout line is forced low until the
Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the
sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition
is internally looped back to the receiver.
Value Description
0 no break
1 break serial output spacing
RW 0x0