agent_ccc0_ccc_llc_control

         When the CCC is connected to a Last Level Cache, it has some unique programmable features that allows the two to interact more closely.  This register allows programmable control of these features.
The CM bit is the enable for the Cache Maintenance Operation propagation.  A Cache Maintenance Operation flushes or invalidates a cache line from the coherency domain.  This can allow interaction with non-coherent devices that access the slave directly.  Since a Last Level Cache can hold additional data, it may be necessary to flush or invalidate lines from the LLC to memory.  When this register bit is set, the CCC will propagate any Cache Maintenance Operations to the LLC, where the cache can take the specified action.  When this bit is set to zero, the Cache Maintenance Operations will not be propagated.
The WE bit is the enable for Write Evict propagation.  In ACE protocol rev E, the WriteEvict command was created in order to write clean data to a downstream cache, such as the Last Level Cache.  This allows the cache to only allocate a line when it is dropped by one of the ACE masters, allowing a better utilization of RAM storage.  When the WE bit is set to 1, the WriteEvict will be propagated from the CCC to the LLC.  If set to 0, the WriteEvict will drop the data and only update the CCC directory to indicate that the master has given up its copy of the line.

      
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF7030040

Size: 64

Offset: 0x30040

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

UNSD_63_2

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

UNSD_63_2

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD_63_2

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UNSD_63_2

RO 0x0

CM

RW 0x0

WE

RW 0x0

agent_ccc0_ccc_llc_control Fields

Bit Name Description Access Reset
63:2 UNSD_63_2
                 
                 
RO 0x0
1 CM
                 1'b1: A value of 1 indicates cache maintenance operations will be propogated from CCC
1'b0: A value of 0 indicates cache maintenance operations will not propogate past CCC

                 
RW 0x0
0 WE
                 1'b1: A value of 1 indicates WriteEvict will be forwarded to LLC
1'b0: A value of 0 indicates WriteEvict will not be forwarded

                 
RW 0x0