mpu_ace

         This is MPU control register

Module Instance	Base Address	Register Address
`i_sys_mgr_core`	`0xFFD12000`	`0xFFD12014`

Size: 32

Offset: 0x14

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`			`arqos` `RW 0x2`					`Reserved`				`awqos` `RW 0x2`

mpu_ace Fields

Bit

Name

Description

Access

Reset

12:8

arqos

Sets the Priority of all write transactions originating from the MPU ACE socket. Priority is used by interconnects and memory scheduler on the HPS. Defaults to the highest priority (>=2)

Value	Description
0	LOW
1	MED
2	HIGH

RW

0x2

3:0

awqos

Sets the Priority of all write transactions originating from the MPU ACE socket. Priority is used by interconnects and memory scheduler on the HPS. Defaults to the highest priority (>=2)

Value	Description
0	LOW
1	MED
2	HIGH

RW

0x2