ddr_scheduler_ccu_mem0_I_main_QosGenerator Summary

Base Address: 0xF8022080

Register

Address Offset

Bit Fields
soc_ddr_scheduler_inst_0_ccu_mem0_I_main_QosGenerator

ccu_mem0_I_main_QosGenerator_Id_CoreId

0x0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CORECHECKSUM

RO 0x89B4D7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CORECHECKSUM

RO 0x89B4D7

CORETYPEID

RO 0x4

ccu_mem0_I_main_QosGenerator_Id_RevisionId

0x4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FLEXNOCID

RO 0x148

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FLEXNOCID

RO 0x148

USERID

RO 0x0

ccu_mem0_I_main_QosGenerator_Priority

0x8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MARK

RO 0x1

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

P1

RW 0x0

Reserved

P0

RW 0x0

ccu_mem0_I_main_QosGenerator_Mode

0xC

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

MODE

RW 0x1

ccu_mem0_I_main_QosGenerator_Bandwidth

0x10

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

BANDWIDTH

RW 0xBFE

ccu_mem0_I_main_QosGenerator_Saturation

0x14

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

SATURATION

RW 0x8

ccu_mem0_I_main_QosGenerator_ExtControl

0x18

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

INTCLKEN

RW 0x0

EXTTHREN

RW 0x0

SOCKETQOSEN

RW 0x0