intrsts
Interrupt Pending Status after the interrupt masks.
Set by hardware and read by software.
Sticky behavior. Once set by hardware, the bit will remain set, till cleared by software by writing to intrclr register.
The status for a particular bit would be read as 0, if the curresponding mask bit is set.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_clk_mgr_clkmgr | 0xFFD10000 | 0xFFD10018 |
Size: 32
Offset: 0x18
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
perlocklost 0x0 |
mainlocklost 0x0 |
perlockachieved 0x0 |
mainlockachieved 0x0 |
|||||||||||
intrsts Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 3 | perlocklost |
Pending status for periph PLL lock lost interrupt after intr mask |
RO | 0x0 |
| 2 | mainlocklost |
Pending status for main PLL lock lost interrupt after intr mask |
RO | 0x0 |
| 1 | perlockachieved |
Pending status for periph PLL lock achieved interrupt after intr mask |
RO | 0x0 |
| 0 | mainlockachieved |
Pending status for main PLL lock achieved interrupt after intr mask |
RO | 0x0 |