reg_ctrlcfg1

iohmc_ctrl_mmr_top_inst.cfg_dbc3_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.

iohmc_ctrl_mmr_top_inst.cfg_dbc2_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.

iohmc_ctrl_mmr_top_inst.cfg_dbc1_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.

iohmc_ctrl_mmr_top_inst.cfg_dbc0_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.

iohmc_ctrl_mmr_top_inst.cfg_ctrl_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.

iohmc_ctrl_mmr_top_inst.cfg_dqstrk_en
Name:DQS Tracking Enable
Description:Enables DQS tracking in the PHY.
1’b1 – Enable Long/Short DQS Tracking
Post-REFRESH-EXIT – Refer to cfg_short_dqstrk_ctrl_en
Post-SELFREFRESH-EXIT – IOPHYSEQ performs Long DQS Tracking
1’b0 – Disable DQS Tracking

iohmc_ctrl_mmr_top_inst.cfg_starve_limit[5:0]
Name:Starvation Limit
Description:Specifies the number of DRAM burst transactions an individual transaction will allow to reorder ahead of it before its priority is raised in the memory controller.

iohmc_ctrl_mmr_top_inst.cfg_reorder_read
Name:Read Command Reorder Enable
Description:This bit controls whether the controller can re-order read command to.  1’b0 – Disable, 1’b1 – Enable

iohmc_ctrl_mmr_top_inst.cfg_dbc3_reorder_rdata
Name:DBC3 – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.

iohmc_ctrl_mmr_top_inst.cfg_dbc2_reorder_rdata
Name:DBC2 – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.

iohmc_ctrl_mmr_top_inst.cfg_dbc1_reorder_rdata
Name:DBC1 – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.

iohmc_ctrl_mmr_top_inst.cfg_dbc0_reorder_rdata
Name:DBC0 – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.

iohmc_ctrl_mmr_top_inst.cfg_ctrl_reorder_rdata
Name:CTRL – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.

iohmc_ctrl_mmr_top_inst.cfg_reorder_data
Name:Column Command Reorder Enable
Description:This bit controls whether the controller can re-order operations to optimize SDRAM bandwidth.  It should generally be set to a one.

iohmc_ctrl_mmr_top_inst.cfg_dbc3_enable_ecc
Name:DBC3 – ECC Enable
Description:Enable the generation and checking of ECC.

iohmc_ctrl_mmr_top_inst.cfg_dbc2_enable_ecc
Name:DBC2 – ECC Enable
Description:Enable the generation and checking of ECC.

iohmc_ctrl_mmr_top_inst.cfg_dbc1_enable_ecc
Name:DBC1 – ECC Enable
Description:Enable the generation and checking of ECC.

iohmc_ctrl_mmr_top_inst.cfg_dbc0_enable_ecc
Name:DBC0 – ECC Enable
Description:Enable the generation and checking of ECC.

iohmc_ctrl_mmr_top_inst.cfg_ctrl_enable_ecc
Name:Ctrl – ECC Enable
Description:Enable the generation and checking of ECC.

iohmc_ctrl_mmr_top_inst.cfg_addr_order[1:0]
Name:Address Interleaving Order
Description:The only allowed value for address interleaving is 00=chip, row, bank, column. All other encodings are reserved.

iohmc_ctrl_mmr_top_inst.cfg_dbc3_burst_length[4:0]
Name:DBC3 – DRAM Memory Burst Length
Description:Configures burst length for DBC3.  Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type.  For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary “01000”).