TBBCNT

         
Name: Transferred Host to BIU-FIFO Byte Count Register
Size: 32 bits
Address Offset: 0x60
Read/write access: read
      
Module Instance Base Address Register Address
sdm_i_sdmmc_sdmmc_block 0xFF8D1000 0xFF8D1060

Size: 32

Offset: 0x60

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TRANS_FIFO_BYTE_COUNT

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TRANS_FIFO_BYTE_COUNT

RO 0x0

TBBCNT Fields

Bit Name Description Access Reset
31:0 TRANS_FIFO_BYTE_COUNT
Number of bytes transferred between Host/DMA memory and BIU FIFO.
In 32-bit or 64-bit AMBA data-bus-width modes, register should be accessed in full to avoid read-coherency problems.In 16-bit AMBA data-bus-width mode, internal 16-bit coherency register is implemented. User should first read lower 16 bits and then higher 16 bits. When reading lower 16 bits, higher 16 bits of counter are stored in temporary register. When higher 16 bits are read, data from temporary register is supplied.
Both TCBCNT and TBBCNT share same coherency register.
RO 0x0