fpga2sdram_manager_main_SidebandManager_FlagOutClr0 

         FPGA2SDRAM Manager Sideband Manager Flag Out Clear 0 Register
Module Instance Base Address Register Address
soc_ddr_scheduler_inst_0_fpga2sdram_manager_main_SidebandManager 0xF8024000 0xF8024054

Size: 32

Offset: 0x54

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FPGA2SDRAM2_FORCE_DRAIN_CLR

RW 0x0

FPGA2SDRAM2_ENABLE_CLR

RW 0x0

FPGA2SDRAM2_IDLEREQ_CLR

RW 0x0

FPGA2SDRAM1_FORCE_DRAIN_CLR

RW 0x0

FPGA2SDRAM1_ENABLE_CLR

RW 0x0

FPGA2SDRAM1_IDLEREQ_CLR

RW 0x0

FPGA2SDRAM0_FORCE_DRAIN_CLR

RW 0x0

FPGA2SDRAM0_ENABLE_CLR

RW 0x0

FPGA2SDRAM0_IDLEREQ_CLR

RW 0x0

fpga2sdram_manager_main_SidebandManager_FlagOutClr0 Fields

Bit Name Description Access Reset
8 FPGA2SDRAM2_FORCE_DRAIN_CLR 
FlagOut Clr register #8.FPGA2SDRAM2_FORCE_DRAIN_CLR
 RW 0x0
7 FPGA2SDRAM2_ENABLE_CLR 
FlagOut Clr register #7.FPGA2SDRAM2_ENABLE_CLR
 RW 0x0
6 FPGA2SDRAM2_IDLEREQ_CLR 
FlagOut Clr register #6.FPGA2SDRAM2_IDLEREQ_CLR
 RW 0x0
5 FPGA2SDRAM1_FORCE_DRAIN_CLR 
FlagOut Clr register #5.FPGA2SDRAM1_FORCE_DRAIN_CLR
 RW 0x0
4 FPGA2SDRAM1_ENABLE_CLR 
FlagOut Clr register #4.FPGA2SDRAM1_ENABLE_CLR
 RW 0x0
3 FPGA2SDRAM1_IDLEREQ_CLR 
FlagOut Clr register #3.FPGA2SDRAM1_IDLEREQ_CLR
 RW 0x0
2 FPGA2SDRAM0_FORCE_DRAIN_CLR 
FlagOut Clr register #2.FPGA2SDRAM0_FORCE_DRAIN_CLR
 RW 0x0
1 FPGA2SDRAM0_ENABLE_CLR 
FlagOut Clr register #1.FPGA2SDRAM0_ENABLE_CLR
 RW 0x0
0 FPGA2SDRAM0_IDLEREQ_CLR 
FlagOut Clr register #0.FPGA2SDRAM0_IDLEREQ_CLR
 RW 0x0