gmacgrp_debug 

          Register 9 (Debug Register)   

The Debug register gives the status of all main modules of the transmit and receive data-paths and the FIFOs. An all-zero status indicates that the MAC is in idle state (and FIFOs are empty) and no activity is going on in the data-paths.

Note:  

The reset values, given for the Debug register, are valid only if the  following clocks are present during the reset operation:  
 * clk_csr_i, clk_app_i, hclk_i, or aclk_i  
 * clk_tx_i 
 * clk_rx_i
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800024
i_emac_emac1 0xFF802000 0xFF802024
i_emac_emac2 0xFF804000 0xFF804024

Size: 32

Offset: 0x24

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_26

RO 0x0

txstsfsts

RO 0x0

txfsts

RO 0x0

reserved_23

RO 0x0

twcsts

RO 0x0

trcsts

RO 0x0

txpaused

RO 0x0

tfcsts

RO 0x0

tpests

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15_10

RO 0x0

rxfsts

RO 0x0

reserved_7

RO 0x0

rrcsts

RO 0x0

rwcsts

RO 0x0

reserved_3

RO 0x0

rfcfcsts

RO 0x0

rpests

RO 0x0

gmacgrp_debug Fields

Bit Name Description Access Reset
31:26 reserved_31_26 
Reserved
 RO 0x0
25 txstsfsts 
MTL TxStatus FIFO Full Status

When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
24 txfsts 
MTL Tx FIFO Not Empty Status

When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
23 reserved_23 
Reserved
 RO 0x0
22 twcsts 
MTL Tx FIFO Write Controller Active Status

When high, this bit indicates that the MTL Tx FIFO Write Controller is active and transferring data to the Tx FIFO.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
21:20 trcsts 
MTL Tx FIFO Read Controller Status

This field indicates the state of the Tx FIFO Read Controller:
 * 00: IDLE state
 * 01: READ state (transferring data to MAC transmitter)
 * 10: Waiting for TxStatus from MAC transmitter
 * 11: Writing the received TxStatus or flushing the Tx FIFO
Value Description
0x0 IDLE
0x1 READSTATE
0x2 WAITTXSTAT
0x3 WRTXSTAT
RO 0x0
19 txpaused 
MAC transmitter in PAUSE

When high, this bit indicates that the MAC transmitter is in the PAUSE condition (in the full-duplex only mode) and hence does not schedule any frame for transmission.
Value Description
0x0 DISABLE
0x1 ENABLED
RO 0x0
18:17 tfcsts 
MAC Transmit Frame Controller Status

This field indicates the state of the MAC Transmit Frame Controller module:
 * 00: IDLE state
 * 01: Waiting for Status of previous frame or IFG or backoff period to be over
 * 10: Generating and transmitting a PAUSE control frame (in the full-duplex mode)
 * 11: Transferring input frame for transmission
Value Description
0x0 IDLE
0x1 WAITIFG
0x2 XTPAUSE
0x3 XTINFRM
RO 0x0
16 tpests 
MAC GMII or MII Transmit Protocol Engine Status

When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state.
Value Description
0x0 DISABLED
0x1 ENABLED
RO 0x0
15:10 reserved_15_10 
Reserved
 RO 0x0
9:8 rxfsts 
MTL Rx FIFO Fill-level Status

This field gives the status of the fill-level of the Rx FIFO: 
 * 00: Rx FIFO Empty
 * 01: Rx FIFO fill level is below the flow-control deactivate threshold
 * 10: Rx FIFO fill level is above the flow-control activate threshold
 * 11: Rx FIFO Full
Value Description
0x0 RXFIFOEMPTY
0x1 RXFIFOBELLVL
0x2 RXFIFOABLVL
0x3 RXFIFOFULL
RO 0x0
7 reserved_7 
Reserved
 RO 0x0
6:5 rrcsts 
MTL Rx FIFO Read Controller State

This field gives the state of the Rx FIFO read Controller:
 * 00: IDLE state
 * 01: Reading frame data
 * 10: Reading frame status (or timestamp)
 * 11: Flushing the frame data and status
Value Description
0x0 IDLE
0x1 RDFRAMEDATA
0x2 RDFRAMESTAT
0x3 FLUSHFRDS
RO 0x0
4 rwcsts 
MTL Rx FIFO Write Controller Active Status

When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
3 reserved_3 
Reserved
 RO 0x0
2:1 rfcfcsts 
MAC Receive Frame Controller FIFO Status

When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
0 rpests 
MAC GMII or MII Receive Protocol Engine Status

When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0