ECCCTRL2

         ECC control 2.
This bit is used to set the initialize the memory and ecc to a known value

Module Instance	Base Address	Register Address
`soc_hmc_adp_csr_inst_0_ocp_slv_block`	`0xF8011000`	`0xF8011104`

Size: 32

Offset: 0x104

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`															`OVRW_RB_ECC_EN` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`RMW_EN` `0x0`	`Reserved`							`AUTOWB_EN` `0x0`

ECCCTRL2 Fields

Bit

Name

Description

Access

Reset

OVRW_RB_ECC_EN

Overwrite the read-back ecc code during RMW process if DBE is detected.
1'b0: write the read-back ECC from RMW process if derr is detected. Default value after reset.
1'b1: write of 1 will overwrite the ECC overwrite feature.

Value	Description
0	DISABLE
1	ENABLE

RW

0x0

RMW_EN

Enable read modify write logic.
When ECC is enabled and sub word accesses require correct ECC to be calculated, this bit should be enabled. RMW_EN bit should be disabled when ECC_EN is disabled.
1'b0: disable RMW logic. Default value after reset.
1'b1: enable RMW logic.

Value	Description
0	DISABLE
1	ENABLE

RW

0x0

AUTOWB_EN

Enable auto write back correction feature.
When serr is detected on outgoing reads, HMC adaptor schedules the corrected data and ECC to the written to the DDR memory. This bit enables auto correction of DDR memory.
1'b0: disable auto WB drop correction. Default value after reset.
1'b1: enable auto WB drop correction.

Value	Description
0	DISABLE
1	ENABLE

RW

0x0