DIAGINTTEST
Enable diagnostic errors
| Module Instance | Base Address | Register Address |
|---|---|---|
| soc_hmc_adp_csr_inst_0_ocp_slv_block | 0xF8011000 | 0xF8011124 |
Size: 32
Offset: 0x124
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
TADDRPAR 0x0 |
Reserved |
TADDRMTC 0x0 |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
TDERRA 0x0 |
Reserved |
TSERRA 0x0 |
||||||||||||
DIAGINTTEST Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 24 | TADDRPAR |
Diagnostic of address parity of DDR4. This bit is used to test the address parity error path. 1'b0: Disables generating address match bus error as part of the transaction. 1'b1: When this bit is set to 1, derr_req signal is generated to the system manager when the ECC decoder detects an ecc address parity error. By writing to this bit, ADDRPARFLG bit will be pending. Write of one to ADDRPARFLG will clear this bit. SW needs to explicitly write to DERRPENA to clear it.
|
RW | 0x0 | ||||||
| 16 | TADDRMTC |
Diagnostic enable of Address mismatch error. This bit is used to flag that the last transaction was flagged with address mismatch error. 1'b0: Disables generating address match bus error as part of the transaction. 1'b1: When this bit is set to 1, derr_req signal is generated to the system manager when the ECC decoder detects a ecc address mismatch. By writing to this bit, ADDRMTCFLG bit will be pending. Write of one to ADDRMTCFLG will clear this bit. SW needs to explicitly write to DERRPENA to clear it.
|
RW | 0x0 | ||||||
| 8 | TDERRA |
Diagnostic enable of Double-bit error. This bit is used to test double-bit error. 1'b0: Write of zero has no effect. 1'b1: When this bit is set to 1, derr_req signal is generated to the system manager when the ECC decoder detects a double-bit error. By writing to this bit, DERRBUSFLG bit will be pending. Write of one to DERRBUSFLG will clear this bit. SW needs to explicitly write to DERRPENA to clear it.
|
RW | 0x0 | ||||||
| 0 | TSERRA |
This bit is used to test a single-bit error. 1'b0: Write of zero has no effect. 1'b1: When this bit is set to 1, serr_req signal is generated to the system manager when the ECC decoder detects a single-bit error. By writing to this bit, SERRPENA bit will be pending. Write of one to SERRPENA will clear this bit.
|
RW | 0x0 |