dbgmodrst 

         The DBGMODRST register is used by software to control module resets.  

When software writes the csdap_rst bit to 1, the RstMgr hardware will assert both the csdap_rst and the dbg_rst resets, and then release just the dbg_rst after 16 boot clock cycles . The csdap_rst will remain asserted until software clears the csdap_rst bit.
 
When software writes the dbg_rst bit to 1, the RstMgr hardware will assert both the csdap_rst and the dbg_rst, and then release just the csdap_rst after 16 boot clock cycles. The dbg_rst will remain asserted until software clears the dbg_rst bit.
 
When software writes 1 to both the cs_dap_rst and  the dbg_rst, the RstMgr hardware will assert both the cs_dap_rst and the dbg_rst, and then release both the csdap_rst and dbg_rst after 16 boot clock cycles. Software does not need to clear either bit.
 
All fields are only reset by a cold reset.

Note: It is recommended that software performs the handshake(debug_l3noc)  by using the corresponding bits of "hdsken" and "hdskreq" registers before resetting dap or debug logic. SW should poll the "debug_l3noc_ack" bit and implement its own timer. Only after the handshake is completed, SW should assert these resets.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD11000 0xFFD1103C

Size: 32

Offset: 0x3C

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

csdap_rst

RW 0x0

dbg_rst

RW 0x0

dbgmodrst Fields

Bit Name Description Access Reset
1 csdap_rst 
Resets logic located  in the DAP domain.
 RW 0x0
0 dbg_rst 
Resets logic located  in the debug domain.
 RW 0x0