per0modrst 

         The PER0MODRST register is used by software to control module resets for Peripheral Group and Fast Peripheral Group.  Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset signals are asserted for the appropriate length of time and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that would prevent software from de-asserting the module reset signal. 

Software writes a bit to 1 to assert the module reset signal and to 0 to de-assert the module reset signal.
All fields are reset by a cold reset. All fields are also reset by a warm reset.
The reset value of all fields is 1. This holds the corresponding module in reset until software is ready to release the module from reset by writing 0 to its field.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD11000 0xFFD11024

Size: 32

Offset: 0x24

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

dmaif7

RW 0x1

dmaif6

RW 0x1

dmaif5

RW 0x1

dmaif4

RW 0x1

dmaif3

RW 0x1

dmaif2

RW 0x1

dmaif1

RW 0x1

dmaif0

RW 0x1

Reserved

emacptp

RW 0x1

dmaocp

RW 0x1

spis1

RW 0x1

spis0

RW 0x1

spim1

RW 0x1

spim0

RW 0x1

dma

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

sdmmcocp

RW 0x1

Reserved

nandocp

RW 0x1

usb1ocp

RW 0x1

usb0ocp

RW 0x1

emac2ocp

RW 0x1

emac1ocp

RW 0x1

emac0ocp

RW 0x1

sdmmc

RW 0x1

Reserved

nand

RW 0x1

usb1

RW 0x1

usb0

RW 0x1

emac2

RW 0x1

emac1

RW 0x1

emac0

RW 0x1

per0modrst Fields

Bit Name Description Access Reset
31 dmaif7 
Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA Controller
 RW 0x1
30 dmaif6 
Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA Controller
 RW 0x1
29 dmaif5 
Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA Controller
 RW 0x1
28 dmaif4 
Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA Controller
 RW 0x1
27 dmaif3 
Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA Controller.
 RW 0x1
26 dmaif2 
Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA Controller.
 RW 0x1
25 dmaif1 
Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA Controller
 RW 0x1
24 dmaif0 
Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA Controller.
 RW 0x1
22 emacptp 
Resets EMAC PTP.
 RW 0x1
21 dmaocp 
Resets DMA Controller ECC OCP DIagnostics modules.
 RW 0x1
20 spis1 
Resets SPIS1 controller.
 RW 0x1
19 spis0 
Resets SPIS0 controller.
 RW 0x1
18 spim1 
Resets SPIM1 controller.
 RW 0x1
17 spim0 
Resets SPIM0 controller.
 RW 0x1
16 dma 
Resets DMA controller.
 RW 0x1
15 sdmmcocp 
Resets SDMMC ECC OCP DIagnostics modules.
 RW 0x1
13 nandocp 
Resets NAND ECC OCP DIagnostics modules.
 RW 0x1
12 usb1ocp 
Resets USB1 ECC OCP DIagnostics modules.
 RW 0x1
11 usb0ocp 
Resets USB0 ECC OCP DIagnostics modules.
 RW 0x1
10 emac2ocp 
Resets EMAC0 ECC OCP DIagnostics modules.
 RW 0x1
9 emac1ocp 
Resets EMAC1 ECC OCP DIagnostics modules.
 RW 0x1
8 emac0ocp 
Resets EMAC0 ECC OCP DIagnostics modules.
 RW 0x1
7 sdmmc 
Resets SD/MMC controller.
 RW 0x1
5 nand 
Resets NAND flash controller.
 RW 0x1
4 usb1 
Resets USB1.
 RW 0x1
3 usb0 
Resets USB0.
 RW 0x1
2 emac2 
Resets EMAC2.
 RW 0x1
1 emac1 
Resets EMAC1.
 RW 0x1
0 emac0 
Resets EMAC0.
 RW 0x1