GPIO_DEBOUNCE

         Name: Debounce enable
Size: 1-32 bits
Address Offset: 0x48
Read/Write Access: Read/Write
      
Module Instance Base Address Register Address
sdm_gpio_DW_apb_gpio_addr_block 0xFF8D0300 0xFF8D0348

Size: 32

Offset: 0x48

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

GPIO_DEBOUNCE

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPIO_DEBOUNCE

RW 0x0

GPIO_DEBOUNCE Fields

Bit Name Description Access Reset
23:0 GPIO_DEBOUNCE
Controls whether an external signal that is the source
of an interrupt needs to be debounced to remove any
spurious glitches. Writing a 1 to a bit in this register
enables the debouncing circuitry. A signal must be
valid for two periods of an external clock before it is
internally processed.
0  No debounce (default)
1  Enable debounce

DO NOT PUBLISH BELOW THIS LINE
For internal usage only, [0:18] for SDM, [0:23] for HPS
Value Description
0x0 No debounce
0x1 Enable debounce
RW 0x0