firewall_ddr_scheduler_mpfe_scr Summary

DDR Scheduler Security Control Registers (SCR)

Base Address: 0xF8020000

Register

Address Offset

Bit Fields
soc_noc_fw_mpfe_csr_inst_0_mpfe_scr

hmc_register

0x0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

axi_ap

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fpga2soc

RW 0x0

Reserved

mpu

RW 0x0

hmc_adaptor_register

0x4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

axi_ap

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fpga2soc

RW 0x0

Reserved

mpu

RW 0x0

fpga2sdram_sidebandmgr

0x18

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

axi_ap

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fpga2soc

RW 0x0

Reserved

mpu

RW 0x0

noc_probes

0x14

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

axi_ap

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fpga2soc

RW 0x0

Reserved

mpu

RW 0x0

noc_scheduler_csr

0x8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

axi_ap

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fpga2soc

RW 0x0

Reserved

mpu

RW 0x0

noc_qos

0x10

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

axi_ap

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fpga2soc

RW 0x0

Reserved

mpu

RW 0x0