pllc0

         Channel C0 frequency settings for the periph PLL
      
Module Instance Base Address Register Address
i_clk_mgr_perpllgrp 0xFFD100A4 0xFFD100F4

Size: 32

Offset: 0x50

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

en

RW 0x1

bypas

RW 0x0

phrst

RW 0x0

phinc

RW 0x0

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

div

RW 0x2

pllc0 Fields

Bit Name Description Access Reset
27 en
PLL channel 0 output enable; the output is muted before lock signal is asserted, regardless of the value; after lock is asserted, it is glitch-free enable ock_vpll_pr1, if enabled 
Value Description
0 DISABLE
1 ENABLE
RW 0x1
26 bypas
PLL channel 0 output bypass; before lock, it is muted, regardless of its value. After lock, if enabled and bypass=1, this outputs refclk. 
Value Description
0 UNBYPASS
1 BYPASS
RW 0x0
25 phrst
If ictl_vpll_pr1_phrst_a=1'b1, the phase of PLLC0 clock is reset to default phase as the PLL is just started. 
Value Description
0 RSTDEASSERT
1 RSTASSERT
RW 0x0
24 phinc
When a positive edge is induced, one of the positive edges of PLLC0 clock is pushed out by 1/8th of VCO period. 
Value Description
0 UNPUSH
1 PUSH
RW 0x0
7:0 div
PLL channel 0 divider ratio in binary code; Can be dynamically updated after lock signal is asserted, glitch-free from 8'd3 to 8'd255; could encounter glitches for 8'd1 and 8d'2 cases. 

RW 0x2