DRAMADDRWIDTH 

         DRAM address bit width
Module Instance Base Address Register Address
soc_hmc_adp_csr_inst_0_ocp_slv_block 0xF8011000 0xF80110E0

Size: 32

Offset: 0xE0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

CFG_CS_ADDR_WIDTH

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CFG_BANK_GROUP_ADDR_WIDTH

0x0

CFG_BANK_ADDR_WIDTH

0x0

CFG_ROW_ADDR_WIDTH

0x0

CFG_COL_ADDR_WIDTH

0x0

DRAMADDRWIDTH Fields

Bit Name Description Access Reset
18:16 CFG_CS_ADDR_WIDTH 
Chip Address Bits
The number of chip select address bits for the memory devices in your memory interface.
 RW 0x0
15:14 CFG_BANK_GROUP_ADDR_WIDTH 
DRAM Bank Group Address Bits
The number of bank group address bits for t	he memory devices in your memory interface.
 RW 0x0
13:10 CFG_BANK_ADDR_WIDTH 
DRAM Bank Address Bits
The number of bank address bits for the memory devices in your memory interface.
 RW 0x0
9:5 CFG_ROW_ADDR_WIDTH 
DRAM Row Address Bits
The number of row address bits for the memory devices in your memory interface.
 RW 0x0
4:0 CFG_COL_ADDR_WIDTH 
DRAM Column Address Bits
The number of column address bits for the memory devices in your memory interface.
RW 0x0