SMMU_CB4_TCR_lpae

         The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
      
Note: For register and programming information, please refer to the Arm® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA024030

Size: 32

Offset: 0x24030

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EAE

RW 0x0

NSCFG1_TG1

RW 0x0

SH1

RW 0x0

ORGN1

RW 0x0

IRGN1

RW 0x0

EPD1

RW 0x0

A1

RW 0x0

T1SZ_5_3

RW 0x0

T1SZ_2_0_PASIZE

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

NSCFG0_TG0

RW 0x0

SH0

RW 0x0

ORGN0

RW 0x0

IRGN0

RW 0x0

SL0_1_EPD0

RW 0x0

SL0_0

RW 0x0

PD1_T0SZ_5

RW 0x0

S_PD0_T0SZ_4

RW 0x0

T0SZ_3_0

RW 0x0