IC_CLR_INTR

         Name: Clear Combined and Individual Interrupt Register
Size: 1 bit
Address Offset: 0x40
Read/Write Access: Read
      
Module Instance Base Address Register Address
i_i2c_emac_0_DW_apb_i2c_addr_block1 0xFFC02A00 0xFFC02A40
i_i2c_emac_1_DW_apb_i2c_addr_block1 0xFFC02B00 0xFFC02B40
i_i2c_emac_2_DW_apb_i2c_addr_block1 0xFFC02C00 0xFFC02C40

Size: 32

Offset: 0x40

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_CLR_INTR

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IC_CLR_INTR

RO 0x0

CLR_INTR

RO 0x0

IC_CLR_INTR Fields

Bit Name Description Access Reset
31:1 RSVD_IC_CLR_INTR
Reserved bits - Read Only
RO 0x0
0 CLR_INTR
Read this register to clear the combined interrupt,
all individual interrupts, and the IC_TX_ABRT_SOURCE register.
This bit does not clear hardware clearable interrupts but software
clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register
for an exception to clearing IC_TX_ABRT_SOURCE.
Reset value: 0x0
RO 0x0