agent_ccc0_ccc_event_counter_mask 

         This register is used to program the event counter. Each bit of this register enables the performance counter to increment if the event occurs. A value of 1 for a bit indicates that this event should be counted.
If multiple bits are set to 1, the logic will only count if all of the corresponding events occur on the same cycle. This allows for combinations of events, such as a directory miss for a Shared line request. The events that can be counted are all related to directory accesses and occur in the same cycle of the pipeline, so they can be combined easily.
When an event satisfies all of the requirements, the ccc_event_counter_value register will be updated.
A value of 1 indicates that the event is selected for counting. A value of 0 the event is not selected. By default, this register will be set to 0 for all bits, indicating no event counting should occur.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF7030100

Size: 64

Offset: 0x30100

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

UNSD_63_14

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

UNSD_63_14

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD_63_14

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UNSD_63_14

RO 0x0

E13

RW 0x0

E12

RW 0x0

E11

RW 0x0

E10

RW 0x0

E9

RW 0x0

E8

RW 0x0

E7

RW 0x0

E6

RW 0x0

E5

RW 0x0

E4

RW 0x0

E3

RW 0x0

E2

RW 0x0

E1

RW 0x0

E0

RW 0x0

agent_ccc0_ccc_event_counter_mask Fields

Bit Name Description Access Reset
63:14 UNSD_63_14
RO 0x0
13 E13 
                 1'b1: Cache maintenance request being processedin LUP2
RW 0x0
12 E12 
                 1'b1: Directory evict request being processed in LUP2
RW 0x0
11 E11 
                 1'b1: Directory hit and may need snoops in LUP2
RW 0x0
10 E10 
                 1'b1: Request missed in directory in LUP2 cycle
RW 0x0
9 E9 
                 1'b1: Request caused eviction in LUP2 cycle
RW 0x0
8 E8 
                 1'b1: Request for copyback in LUP2 cycle
RW 0x0
7 E7 
                 1'b1: Request for unique line in LUP2 cycle
RW 0x0
6 E6 
                 1'b1: Request for shared line in LUP2 cycle
RW 0x0
5 E5 
                 1'b1: Able to insert evicted entry into directory in LUP2 cycle
RW 0x0
4 E4 
                 1'b1: Locked CleanUnique gets OKAY in LUP2 cycle
RW 0x0
3 E3 
                 1'b1: Locked CleanUnique gets EXOKAY in LUP2 cycle
RW 0x0
2 E2 
                 1'b1: Non-cancelled directory lookup in LUP2 cycle
RW 0x0
1 E1 
                 1'b1: Cancelled directory lookup in LUP2 cycle
RW 0x0
0 E0 
                 1'b1: Valid directory lookup in LUP2 cycle
RW 0x0