sp_timer0 

         Per-Master Security bit for sp_timer0
Module Instance Base Address Register Address
noc_fw_l4_per_l4_per_scr 0xFFD21000 0xFFD21064

Size: 32

Offset: 0x64

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

axi_ap

RW 0x0

Reserved

fpga2soc

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

dma

RW 0x0

Reserved

mpu

RW 0x0

sp_timer0 Fields

Bit Name Description Access Reset
24 axi_ap 
Security bit configuration for transactions from axi_ap to sp_timer0. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
16 fpga2soc 
Security bit configuration for transactions from fpga2soc to sp_timer0. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
8 dma 
Security bit configuration for transactions from dma to sp_timer0. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
0 mpu 
Security bit configuration for transactions from mpu to sp_timer0. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0