SERRCNTREG

         Maximum counter value for single-bit error interrupt
      
Module Instance Base Address Register Address
sdm_ecc_qspi_ecc_registerBlock 0xFFA22000 0xFFA2203C

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SERRCNT

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SERRCNT

0x0

SERRCNTREG Fields

Bit Name Description Access Reset
31:0 SERRCNT
Counter value
RW 0x0