SMMU_CB2_TLBIALL

         Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
      
Note: For register and programming information, please refer to the Arm® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA022618

Size: 32

Offset: 0x22618

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

bits

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

bits

WO 0x0