fpga2sdram0_axi128_I_main_QosGenerator_ExtControl

         External inputs control.
      
Module Instance Base Address Register Address
soc_ddr_scheduler_inst_0_fpga2sdram0_axi128_I_main_QosGenerator 0xF8022100 0xF8022118

Size: 32

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

INTCLKEN

RW 0x0

EXTTHREN

RW 0x0

SOCKETQOSEN

RW 0x0

fpga2sdram0_axi128_I_main_QosGenerator_ExtControl Fields

Bit Name Description Access Reset
2 INTCLKEN
n/a
RW 0x0
1 EXTTHREN
n/a
RW 0x0
0 SOCKETQOSEN
n/a
RW 0x0