This register configures the protection memory characteristics of each protection rule.
Module Instance Base Address Register Address
sdr 0xFFC20000 0xFFC25098

Offset: 0x5098

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0


RW 0x0


RW 0x0


RW 0x0

protruledata Fields

Bit Name Description Access Reset
13 ruleresult

Set this bit to a one to force a protection failure, zero to allow the access the succeed

RW 0x0
12:3 portmask
The bits in this field determine which ports the rule applies to. If a port's bit is set, the rule applies to that port; if the bit is clear, the rule does not apply. The bits in this field correspond to the control ports as follows:
Bit 9 CPU write
Bit 8 L3 write
Bit 7 CPU read
Bit 6 L3 read
Bit 5 FPGA-to-SDRAM port 5
Bit 4 FPGA-to-SDRAM port 4
Bit 3 FPGA-to-SDRAM port 3
Bit 2 FPGA-to-SDRAM port 2
Bit 1 FPGA-to-SDRAM port 1
Bit 0 FPGA-to-SDRAM port 0
RW 0x0
2 validrule

Set to bit to a one to make a rule valid, set to a zero to invalidate a rule.

RW 0x0
1:0 security
Valid security field encodings are:
Value Description
0x0 Rule applies to secure transactions
0x1 Rule applies to non-secure transactions
0x2 or 0x3 Rule applies to secure and non-secure transactions
RW 0x0