This register controls the default protection assignment for a port. Ports which have explicit rules which define regions which are illegal to access should set the bits to pass by default. Ports which have explicit rules which define legal areas should set the bit to force all transactions to fail. Leaving this register to all zeros should be used for systems which do not desire any protection from the memory controller.
Module Instance Base Address Register Address
sdr 0xFFC20000 0xFFC2508C

Offset: 0x508C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

protportdefault Fields

Bit Name Description Access Reset
9:0 portdefault
Determines the default action for specified transactions. When a bit is zero, the specified access is allowed by default. When a bit is one, the specified access is denied by default.
Bit 9 CPU write
Bit 8 L3 write
Bit 7 CPU read
Bit 6 L3 read
Bit 5 Access to FPGA-to-SDRAM port 5
Bit 4 Access to FPGA-to-SDRAM port 4
Bit 3 Access to FPGA-to-SDRAM port 3
Bit 2 Access to FPGA-to-SDRAM port 2
Bit 1 Access to FPGA-to-SDRAM port 1
Bit 0 Access to FPGA-to-SDRAM port 0
RW 0x0