This register controls configuration values which cannot be updated during active transfers. First configure the membl and eccn fields and then re-write these fields while setting the applycfg bit. The applycfg bit is write only.
Module Instance Base Address Register Address
sdr 0xFFC20000 0xFFC2505C

Offset: 0x505C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0


RW 0x0


RW 0x0

staticcfg Fields

Bit Name Description Access Reset
3 applycfg

Write with this bit set to apply all the settings loaded in SDR registers to the memory interface. This bit is write-only and always returns 0 if read.

RW 0x0
2 useeccasdata

This field allows the FPGA ports to directly access the extra data bits that are normally used to hold the ECC code. The interface width must be set to 24 or 40 in the dramifwidth register. If you set this, you must clear the eccen field in the ctrlcfg register.

RW 0x0
1:0 membl

This field specifies the DRAM burst length. The following encodings set the burst length:

  • 0x0= Burst length of 2 clocks
  • 0x1= Burst length of 4 clocks
  • 0x2= Burst length of 8 clocks
  • 0x3= Burst length of 16 clocks

If you program the this field, you must also set the membl field in the ctrlcfg register.

RW 0x0