This register controls the behavior of the low power logic in the controller.
Module Instance Base Address Register Address
sdr 0xFFC20000 0xFFC25014

Offset: 0x5014

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


RW 0x0

lowpwrtiming Fields

Bit Name Description Access Reset
19:16 clkdisablecycles

Set to a the number of clocks after the execution of an self-refresh to stop the clock. This register is generally set based on PHY design latency and should generally not be changed.

RW 0x0
15:0 autopdcycles

The number of idle clock cycles after which the controller should place the memory into power-down mode.

RW 0x0