Timer Module Address Map

Registers in the timer module. The timer IP core supports multiple timers but it is configured for just one timer. The term Timer1 refers to this one timer in the IP core and not the module instance.
Module Instance Base Address
sptimer0 0xFFC08000
sptimer1 0xFFC09000
osc1timer0 0xFFD00000
osc1timer1 0xFFD01000

Timer Module

Register Offset Width Access Reset Value Description
timer1loadcount 0x0 32 RW 0x0 Timer1 Load Count Register
timer1currentval 0x4 32 RO 0x0 Timer1 Current Value Register
timer1controlreg 0x8 32 RW 0x0 Timer1 Control Register
timer1eoi 0xC 32 RO 0x0 Timer1 End-of-Interrupt Register
timer1intstat 0x10 32 RO 0x0 Timer1 Interrupt Status Register
timersintstat 0xA0 32 RO 0x0 Timers Interrupt Status Register
timerseoi 0xA4 32 RO 0x0 Timers End-of-Interrupt Register
timersrawintstat 0xA8 32 RO 0x0 Timers Raw Interrupt Status Register
timerscompversion 0xAC 32 RO 0x3230352A Timers Component Version Register