Used to halt transmission for testing.
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC020A4
uart1 0xFFC03000 0xFFC030A4

Offset: 0xA4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

htx Fields

Bit Name Description Access Reset
0 htx

This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFO's are enabled. Note, if FIFO's are not enabled, the setting of the halt Tx register will have no effect on operation.

Value Description
0x0 Halt Tx disabled
0x1 Halt Tx enabled
RW 0x0