This is a shadow register for the Rx trigger bits (FCR[7:6]).
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC0209C
uart1 0xFFC03000 0xFFC0309C

Offset: 0x9C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

srt Fields

Bit Name Description Access Reset
1:0 srt

This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the Rx trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. It also determines when the uart_dma_rx_req_n signal will be asserted when DMA Mode (FCR[3]) is set to one. The enum below shows trigger levels that are supported.

Value Description
0x0 one character in fifo
0x1 FIFO 1/4 full
0x2 FIFO 1/2 full
0x3 FIFO 2 less than full
RW 0x0