This is a shadow register for the Break bit [6] of the register LCR. This can be used to remove the burden of having to performing a read modify write on the LCR.
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC02090
uart1 0xFFC03000 0xFFC03090

Offset: 0x90

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

sbcr Fields

Bit Name Description Access Reset
0 sbcr

This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the uart_txd line is forced low until the Break bit is cleared. When in Loopback Mode, the break condition is internally looped back to the receiver.

Value Description
0x0 no break
0x1 break serial output spacing
RW 0x0