This is a shadow register for the RTS status (MCR[1]), this can be used to remove the burden of having to performing a read modify write on the MCR.
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC0208C
uart1 0xFFC03000 0xFFC0308C

Offset: 0x8C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

srts Fields

Bit Name Description Access Reset
0 srts

This is used to directly control the Request to Send (uart_rts_n) output. The Request to Send (uart_rts_n) output is used to inform the modem or data set that the UART is read to exchange data. The uart_rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set to one) and FIFO's are enabled (FCR[0] set to one), the uart_rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (uart_rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held inactive high while the value of this location is internally looped back to an input.

Value Description
0x1 uart_rts_n logic0
0x0 uart_rts_n logic1
RW 0x0