tfl

This register is used to specify the number of data entries in the Tx FIFO. Status Bits in USR register monitor the FIFO state.
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC02080
uart1 0xFFC03000 0xFFC03080

Offset: 0x80

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

tfl

RO 0x0

tfl Fields

Bit Name Description Access Reset
4:0 tfl

This indicates the number of data entries in the transmit FIFO.

RO 0x0