Returns interrupt identification and FIFO enable/disable when read.
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC02008
uart1 0xFFC03000 0xFFC03008

Offset: 0x8

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RO 0x0



RO 0x1

iir Fields

Bit Name Description Access Reset
7:6 fifoen

This is used to indicate whether the FIFO's are enabled or disabled.

Value Description
0x0 FIFO disabled
0x3 FIFO enabled
RO 0x0
3:0 id

This indicates the highest priority pending interrupt.

Value Description
0x0 Modem status
0x1 No Interrupt pending
0x2 THR empty
0x4 Receive data available
0x6 Receive line status
0xc Character timeout
RO 0x1