This register controls the amount of time delay (in terms of number of l4_sp_clk clock periods) introduced in the rising edge of SCL relative to SDA changing by holding SCL low when I2C services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (l4_sp_clk)], so if the user requires 10 l4_sp_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the I2C when operating as a slave transmitter.
Module Instance Base Address Register Address
i2c0 0xFFC04000 0xFFC04094
i2c1 0xFFC05000 0xFFC05094
i2c2 0xFFC06000 0xFFC06094
i2c3 0xFFC07000 0xFFC07094

Offset: 0x94

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x64

ic_sda_setup Fields

Bit Name Description Access Reset
7:0 sda_setup

It is recommended that if the required delay is 1000ns, then for an l4_sp_clk frequency of 10 MHz, ic_sda_setup should be programmed to a value of 11.

RW 0x64