The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.
Module Instance Base Address Register Address
i2c0 0xFFC04000 0xFFC04088
i2c1 0xFFC05000 0xFFC05088
i2c2 0xFFC06000 0xFFC06088
i2c3 0xFFC07000 0xFFC07088

Offset: 0x88

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0


RW 0x0

ic_dma_cr Fields

Bit Name Description Access Reset
1 tdmae

This bit enables/disables the transmit FIFO DMA channel.

Value Description
0x0 Transmit DMA disable
0x1 Transmit DMA enabled
RW 0x0
0 rdmae

This bit enables/disables the receive FIFO DMA channel.

Value Description
0x0 Receive DMA disable
0x1 Receive DMA enabled
RW 0x0