This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort that is, TX_ABRT bit is set in the ic_raw_intr_stat register. The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
Module Instance Base Address Register Address
i2c0 0xFFC04000 0xFFC04074
i2c1 0xFFC05000 0xFFC05074
i2c2 0xFFC06000 0xFFC06074
i2c3 0xFFC07000 0xFFC07074

Offset: 0x74

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RO 0x0

ic_txflr Fields

Bit Name Description Access Reset
6:0 txflr

Transmit FIFO Level.Contains the number of valid data entries in the transmit FIFO.

RO 0x0