Enable and disable i2c operation
Module Instance Base Address Register Address
i2c0 0xFFC04000 0xFFC0406C
i2c1 0xFFC05000 0xFFC0506C
i2c2 0xFFC06000 0xFFC0606C
i2c3 0xFFC07000 0xFFC0706C

Offset: 0x6C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0


RW 0x0

ic_enable Fields

Bit Name Description Access Reset
1 txabort

Write 1 does a TX abort. Self cleared on abort completion

RW 0x0
0 enable

Controls whether the I2C is enabled. Software can disable I2C while it is active. However, it is important that care be taken to ensure that I2C is disabled properly. When the I2C is disabled, the following occurs: The TX FIFO and RX FIFO get flushed. Status bits in the IC_INTR_STAT register are still active until I2C goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the I2C stops the current transfer at the end of the current byte and does not acknowledge the transfer. The l4_sp_clk synchronizes pclk and ic_clk. The register ic_enable_status is added to allow software to determine when the hardware has completely shutdown in response to the IC_ENABLE register being set from 1 to 0. Only one register is required to be monitored. Procedure for Disabling I2C 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling period for the highest I2C transfer speed used in the system and supported by I2C. For example, if the highest I2C transfer mode is 400 kb/s, then this ti2c_poll is 25us. 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any repeated polling operation exceeds this maximum value, an error is reported. 3. Execute a blocking thread/process/function that prevents any further I2C master transactions to be started by software, but allows any pending transfers to be completed. 4. The variable POLL_COUNT is initialized to zero. 5. Set IC_ENABLE to 0. 6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant error code. 7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the previous step. Otherwise, exit with a relevant success code.

Value Description
0x0 Disables i2c. TX and RX FIFOs are held in an erased state
0x1 Enables i2c. Software can disable i2c while it is active
RW 0x0