Sets FIFO depth for Interrupt.
Module Instance Base Address Register Address
i2c0 0xFFC04000 0xFFC0403C
i2c1 0xFFC05000 0xFFC0503C
i2c2 0xFFC06000 0xFFC0603C
i2c3 0xFFC07000 0xFFC0703C

Offset: 0x3C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

ic_tx_tl Fields

Bit Name Description Access Reset
7:0 tx_tl

Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in ic_raw_intr_stat register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.

RW 0x0