I2C Receive FIFO Threshold Register.
Module Instance Base Address Register Address
i2c0 0xFFC04000 0xFFC04038
i2c1 0xFFC05000 0xFFC05038
i2c2 0xFFC06000 0xFFC06038
i2c3 0xFFC07000 0xFFC07038

Offset: 0x38

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

ic_rx_tl Fields

Bit Name Description Access Reset
7:0 rx_tl

Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.

RW 0x0