This register controls the threshold value for the transmit FIFO memory. It is impossible to write to this register when the SPI Slave is enabled. The SPI Slave is enabled and disabled by writing to the SPIENR register.
Module Instance Base Address Register Address
spis0 0xFFE02000 0xFFE02018
spis1 0xFFE03000 0xFFE03018

Offset: 0x18

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

txftlr Fields

Bit Name Description Access Reset
7:0 tft

Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. When the number of transmit FIFO entries is less than or equal to this value, the transmit FIFO empty interrupt is triggered.

RW 0x0