This register controls the number of spi_m_clk cycles that are delayed (from the default sample time) before the actual sample of the rxd input occurs. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SPIENR register.
Module Instance Base Address Register Address
spim0 0xFFF00000 0xFFF000F0
spim1 0xFFF01000 0xFFF010F0

Offset: 0xF0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

rx_sample_dly Fields

Bit Name Description Access Reset
6:0 rsd

This register is used to delay the sample of the rxd input port. Each value represents a single spi_m_clk delay on the sample of rxd. Note; If this register is programmed with a value that exceeds 64, a 0 delay will be applied to the receive sample. The maximum delay is 64 spi_m_clk cycles.

RW 0x01
1 Intel recommends to use a non-zero value while supporting the SPI device at frequency greater than 25 MHz. For example,use value 3 to support the N25Q128 SPI device at 50MHz.