This register derives the frequency of the serial clock that regulates the data transfer. The 16-bit field in this register defines the spi_m_clk divider value. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SPIENR register.
Module Instance Base Address Register Address
spim0 0xFFF00000 0xFFF00014
spim1 0xFFF01000 0xFFF01014

Offset: 0x14

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


RW 0x0

baudr Fields

Bit Name Description Access Reset
15:0 sckdv

The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register. If the value is 0, the serial output clock (spim_sclk_out) is disabled. The frequency of the spim_sclk_out is derived from the following equation: Fspim_sclk_out = Fspi_m_clk/SCKDV where SCKDV is any even value between 2 and 65534. For example: for Fspi_m_clk = 3.6864MHz and SCKDV =2 Fspim_sclk_out = 3.6864/2 = 1.8432MHz

RW 0x0