Enables and Disables all SPI operations.
Module Instance Base Address Register Address
spim0 0xFFF00000 0xFFF00008
spim1 0xFFF01000 0xFFF01008

Offset: 0x8

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

spienr Fields

Bit Name Description Access Reset
0 spi_en

Enables and disables all SPI Master operations. When disabled, all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. It is impossible to program some of the SPI Master control registers when enabled.

Value Description
0x0 Disables serial transfer operations
0x1 Enables serial transfer operations
RW 0x0