doepctl0

This is Control OUT Endpoint 0 Control register.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00B00
usb1 0xFFB40000 0xFFB40B00

Offset: 0xB00

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

epena

RO 0x0

epdis

RO 0x0

Reserved

snak

WO 0x0

cnak

WO 0x0

Reserved

stall

RO 0x0

snp

RW 0x0

eptype

RO 0x0

naksts

RO 0x0

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

usbactep

RO 0x1

Reserved

mps

RO 0x0

doepctl0 Fields

Bit Name Description Access Reset
31 epena

When Scatter/Gather DMA mode is enabled, for OUT endpoints this bit indicates that the descriptor structure and data buffer to receive data is setup. When Scatter/Gather DMA mode is disabled(such as for buffer-pointer based DMA mode)this bit indicates that the application has allocated the memory to start receiving data from the USB.The core clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done Endpoint Disabled Transfer Completed In DMA mode, this bit must be Set for the core to transfer SETUP data packets into memory.

Value Description
0x0 No action
0x1 Endpoint Enabled
RO 0x0
30 epdis

The application cannot disable control OUT endpoint 0.

Value Description
0x0 No Endpoint disable
RO 0x0
27 snak

A write to this bit sets the NAK bit for the endpoint.Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set bit on a Transfer Completed interrupt, or after a SETUP is received on the endpoint.

Value Description
0x0 No action
0x1 Set NAK
WO 0x0
26 cnak

A write to this bit clears the NAK bit for the endpoint.

Value Description
0x0 No action
0x1 Clear NAK
WO 0x0
21 stall

The application can only Set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is Set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Value Description
0x0 No Stall
0x1 Stall Handshake
RO 0x0
20 snp

This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory.

Value Description
0x0 Snoop Mode disabled
0x1 Snoop Mode enabled
RW 0x0
19:18 eptype

Hardcoded to 0 for control.

Value Description
0x0 Endpoint Control 0
RO 0x0
17 naksts

When either the application or the core sets this bit, the core stops receiving data, even If there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Value Description
0x0 The core is transmitting non-NAK handshakes based on the FIFO status
0x1 The core is transmitting NAK handshakes on this endpoint
RO 0x0
15 usbactep

This bit is always Set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.

Value Description
0x1 USB Active Endpoint 0
RO 0x1
1:0 mps

The maximum packet size for control OUT endpoint 0 is thesame as what is programmed in control IN Endpoint 0.

Value Description
0x0 64 bytes
0x1 32 bytes
0x2 16 bytes
0x3 8 bytes
RO 0x0